Monte Carlo simulation of implant free InGaAs MOSFET

The performance potential of n-type implant free In0.25Ga0.75As MOSFETs with high-κ dielectric is investigated using ensemble Monte Carlo device simulations. The implant free MOSFET concept takes advantage of the high mobility in III-V materials to allow operation at very high speed and low power. A 100 nm gate length implant free In0.25Ga0.75As MOSFET with a layer structure derived from heterojunction transistors may deliver a drive current of 1800 A/m and transconductance up to 1342 mS/mm. This implant free transistor is then scaled in the both lateral and vertical dimensions to gate lengths of 70 and 50 nm. The scaled devices exhibit continuous improvement in the drive current up to 2600 A/m and 3259 A/m and transconductance of 2076 mS/mm and 3192 mS/mm, respectively. This demonstrates the excellent scaling potential of the implant free MOSFET concept

Effect of oxide interface roughness on the threshold voltage fluctuations in decanano MOSFETs with ultrathin gate oxides

In this paper we use the density gradient (DG) simulation approach to study, in 3D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale. The random 2D surfaces used to represent the interface are constructed using the standard assumptions for the auto-correlation function of the interface. The importance of the quantum mechanical effects when studying oxide thickness fluctuations are illustrated in several simulation examples

Tunnelling and impact ionization in scaled double doped PHEMTs

No abstract available

Gate tunnelling and impact ionisation in sub 100 nm PHEMTs

Impact ionization and thermionic tunnelling as two possible breakdown mechanisms in scaled pseudomorphic high electron mobility transistors (PHEMTs) are investigated by Monte Carlo (MC) device simulations. Impact ionization is included in MC simulation as an additional scattering mechanism whereas thermionic tunnelling is treated in the WKB approximation during each time step in selfconsistent MC simulation. Thermionic tunnelling starts at very low drain voltages but then quickly saturates. Therefore, it should not drastically affect the performance of scaled devices. Impact ionization threshold occurs at greater drain voltages which should assure a reasonable operation voltage scale for all scaled PHEMTs

High performance III-V MOSFETs: a dream close to reality?

We have studied the performance potential of sub 100 nm compound MOSFETs with InGaAs channel and high-k gate insulator, using ensemble Monte Carlo simulations. The results show that such devices could deliver 200-300% increase in the drive current compared to conventional MOSFETs with analogous channel lengths and device structure. This improvement is much higher than the 20-30% drive current increase in similar devices with strained Si channels on virtual SiGe substrates. As a viable solutions to the constant drive current bottleneck anticipated in the International Roadmap for Semiconductors for the next generations of Si MOSFETs it advocates further research in respect of the manufacturability of compound MOSFETs

Effect of impact ionization in scaled pHEMTs

The effect of impact ionization on pseudomorphic high electron mobility transistors is studied using Monte Carlo simulations when these devices are scaled into deep decanano dimensions. The scaling of devices with gate lengths of 120, 90, 70, 50 and 30 nm has been performed in both lateral and vertical directions. The impact ionization is treated as an additional scattering mechanism in the Monte Carlo module. The critical drain voltage, at which device characteristics begin to indicate breakdown, decreases as the gate voltage is lowered. Similarly, the breakdown drain voltage is also found to decrease during the scaling process

RF analysis of aggressively scaled pHEMTs

No abstract avaliable

Self-consistent analysis of carrier-transport and carrier-capture dynamics in quantum cascade intersubband semiconductor lasers

A methodology for the self-consistent analysis of carrier transport and carrier capture aspects of the dynamics of quantum cascade intersubband semiconductor lasers is described in this paper. The approach is used to analyze two prototype quantum cascade lasers. The self-consistent analysis incorporates the calculation of the electron densities and temperatures in each subband, together with the intersubband relaxation time. In the calculation of the relaxation time, we take into account the electron interaction with polar optical and acoustic phonons, as well as electron degeneracy. In addition, we also calculate the capture time, considering backward processes that play a role in the electron transition from an injection into an active region. The calculations indicate intersubband relaxation times of order 1 ps and capture times of order 100 f

Monte Carlo simulations of spin transport in nanoscale In0.7Ga0.3As transistors: temperature and size effects

Spin-based metal-oxide-semiconductor field-effect transistors (MOSFET) with a high-mobility III-V channel are studied using self-consistent quantum corrected ensemble Monte Carlo device simulations of charge and spin transport. The simulations including spin-orbit coupling mechanisms (Dresselhaus and Rashba coupling) examine the electron spin transport in the 25 nm gate length In$_{0.7}$Ga$_{0.3}$As MOSFET. The transistor lateral dimensions (the gate length, the source-to-gate, and the gate-to-drain spacers) are increased to investigate the spin-dependent drain current modulation induced by the gate from room temperature of 300 K down to 77 K. This modulation increases with increasing temperature due to increased Rashba coupling. Finally, an increase of up to 20 nm in the gate length, source-to-gate, or the gate-to-drain spacers increases the spin polarization and enhances the spin-dependent drain current modulation at the drain due to polarization-refocusing effects

Multi-scale Simulations of Metal-Semiconductor Nanoscale Contacts

PublishedAn electron transport simulations via a metal-semiconductor interface is carried out using multi-scale approach by coupling ab-initio calculations with 3D finite element ensemble Monte Carlo technique. The density functional theory calculations of the Mo/GaAs (001) interface show electronic properties of semiconductor dramatically change close to the interface having a strong impact on the transport. Tunnelling barrier lowers and widens due to a band gap narrowing near the interface reducing resistivity by more than one order of magnitude: from 2.1 × 10-8Ω.cm2 to 4.7 × 10-10Ω.cm2. The dependence of electron effective mass from the distance to the interface also plays a role bringing resistivity to 7.9 × 10-10Ω.cm2.This work was supported by the EPSRC grants EP/I010084/1, EP/I009973/1, and HECToR facility computer resource EPSRC grant EP/F067496. PVS was supported by the Royal Society